Analysis of bit errors in NAND and power adjustment
During the NAND chip reading process (physical image extraction) there are internal noise and interference occur, that results to bit errors and data corruption. This problem is particularly critical for TLC flash chips. If physical image extracted with high number of bit errors, the correction through Error Correction Code, that stored in Spare area of page, is impossible. Most of the data become damaged and recovery is not possible.
Below is the picture of one data sector filled with zeros 0x00 (blank NAND chip stores 0xFF). Left picture – sector corrupted by bit errors in NAND, right – good sector corrected through ECC.
Our researches experimentally proved, that lowering power of NAND memory it’s possible to reduce internal noise of NAND and read it with less bit errors (remained errors can be corrected using ECC). For many contemporary chips a significant reduction of bit errors notable when voltage lowered to 2.5 … 1.8V. The voltage level should be adjusted experimentally, starting at standard 3.3V and going down to the limit.
Note: When too low power is applied, NAND chip or reader may hang (the reader may turn on red led and must be replugged). In this case power must be increased on one step.
Evaluation of bit errors made in the Bitmap viewer. Open Dump viewer and enable Bitmap viewer (Hex viewer can be disabled) on the Reader element.
Set correct page size in bitmap viewer by pressing the auto-detection button if available, or type manually.
Browse dump of the NAND chip vertically until some blocks with data appear.
Scroll dump horizontally until you find the Spare are, that looks like a vertical pattern, that being changed from block to block. Spare are usually located after first 512 or 1024 bytes in the page, or at the end of page.
The pictures below shows how Spare area should look like when noise level is acceptable (acceptable bit error rate) and high noise level (innaceptable bit error rate). Those small “bad pixels” or contaminations on vertical lines are bit errors.
Acceptable noise level
High noise level
In case if there’s not much errors with standard power level 3.3V, voltage adjustment is not required. If level of noise too high, the power must be lowered through chip config in reader element, then power ON again.
If errors still persist but less, the power must be lowered step down. Check errors again, until they disappear or minimized. Normally, the range of power when “bad” chip produces less errors is 1.8-2.5V, but it must be detected experimentally. Go as low as possible, until chip or reader hangs. If reader hangs – red light appears – reconneсt it. If chip hangs – the bitmap shows artefacts or white empty space – increase power one step up.