Visual NAND Reconstructor 4.2

• New Read Retry algorithms for the newest 3D TLC chips from Micron, Intel and Hynix!

We’re constantly keeping an eye on the new developments in NAND flash industry and tirelessly working to keep up with it. It has to be said that quality of the latest 3D TLC and tolerance to bit errors is not much different comparing to “old” planar 2D TLC memory chips from the same brands. We have been able to find read retry settings for the newest chips and create fast and efficient algorithms.

 

Result after 3 passes of reread without Read Retry

 

Result after 3 passes of reread with Read Retry

 

 

• New “codeword” reread mode for heavily corrupted dumps

 

Now in case if several codewords (data areas) of the page have been successfully corrected during reread by ECC, they won’t be rewritten altogether with page during the next pass of reread. This approach allows to target only those parts of page which are still corrupted. Due to additional page processing the process work slower than traditional “page” mode.

 

• Existing Read Retry algorithms have been improved

Most of existing Read Retry algorithms for Sandisk, Toshiba and Hynix chips have been improved.
In couple with “codeword mode” and multi-pass reread it is now possible to fix bit errors even in cases where charge leakage/degradation from the memory cells is significant and beyond correctability.